Module Reg
module Raw_name : sig ... endtype t={mutable raw_name : Raw_name.t;stamp : int;mutable typ : Cmm.machtype_component;mutable loc : location;mutable spill : bool;mutable part : int option;mutable interf : t list;mutable prefer : (t * int) list;mutable degree : int;mutable spill_cost : int;mutable visited : bool;}and location=|Unknown|Reg of int|Stack of stack_locationand stack_location=|Local of int|Incoming of int|Outgoing of int
val dummy : tval create : Cmm.machtype_component -> tval createv : Cmm.machtype -> t arrayval createv_like : t array -> t arrayval clone : t -> tval at_location : Cmm.machtype_component -> location -> tval anonymous : t -> boolval name : t -> string
module Set : Stdlib.Set.S with type elt = tmodule Map : Stdlib.Map.S with type key = tval add_set_array : Set.t -> t array -> Set.tval diff_set_array : Set.t -> t array -> Set.tval inter_set_array : Set.t -> t array -> Set.tval disjoint_set_array : Set.t -> t array -> boolval set_of_array : t array -> Set.tval reset : unit -> unitval all_registers : unit -> t listval num_registers : unit -> intval reinit : unit -> unit